EPCS64 Altera Corporation, EPCS64 Datasheet - Page 27

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Figure 4–18. AS Configuration Timing
Altera Corporation
July 2004
Notes to
(1)
(2)
CONF_DONE
f
f
t
t
t
t
t
CLK
C L K
CH
CL
H
SU
POR
Table 4–14. Timing Parameters for AS Configuration
INIT_DONE
nCONFIG
nSTATUS
User I/O
DATA0
ASDO
nCSO
DCLK
These values are preliminary
Only the EPCS16 and EPCS64 devices support a DCLK frequency up to 40 MHz.
Symbol
Table
4–14:
t
POR
DCLK
DCLK
(1)
DCLK
DCLK
Data hold time after rising edge on
Data set up time before rising edge on
POR delay
Read Address
frequency from Cyclone FPGA
frequency from Stratix II or Cyclone II FPGA
high time
low time
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Figure 4–18
scheme using a serial configuration device.
Table 4–14
t
SU
t
H
bit N
Parameter
Core Version a.b.c variable
shows the timing parameters for AS configuration mode.
shows the timing waveform for FPGA AS configuration
bit N − 1
DCLK
DCLK
bit 1
t
CH
bit 0
t
CL
Configuration Handbook, Volume 2
20
Min
14
10
25
25
0
5
(2)
136 Cycles
26
Typ
17
13
(2)
40
Max
100
20
20
(2)
User Mode
MHz
MHz
MHz
Unit
ms
ns
ns
ns
ns
4–27