EPCS64 Altera Corporation, EPCS64 Datasheet - Page 23

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Figure 4–15. Erase Sector Operation Timing Diagram
Power &
Operation
Altera Corporation
July 2004
DCLK
ASDI
nCS
0
1
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
The erase sector operation is implemented by first driving nCS low, then
shifting in the erase sector operation code and the three address bytes of
the chosen sector on the ASDI pin. The three address bytes for the erase
sector operation can be any address inside the specified sector. (See
Tables 4–6
after the eighth bit of the erase sector operation code has been latched in.
Figure 4–15
Immediately after the device drives nCS high, the self-timed erase sector
cycle is initiated. The self-timed erase sector cycle usually takes 2 s for
EPCS1 and EPCS4 devices and is guaranteed to be less than 3 s for both
serial configuration devices. You must account for this amount of delay
before the memory contents can be accessed. Alternatively, you can check
the write in progress bit in the status register by executing the read status
operation while the erase cycle is in progress. The write in progress bit is
1 during the self-timed erase cycle and is 0 when it is complete. The write
enable latch bit in the status register is reset to 0 before the erase cycle is
complete.
This section describes the power modes, power-on reset (POR) delay,
error detection, and initial programming state of serial configuration
devices.
Power Mode
Serial configuration devices support active power and standby power
modes. When nCS is low, the device is enabled and is in active power
mode. The FPGA is configured while in active power mode. When nCS is
high, the device is disabled but could remain in active power mode until
all internal cycles have completed (such as write or erase operations). The
serial configuration device then goes into stand-by power mode. The I
2
Operation Code
3
Core Version a.b.c variable
4
and
shows the timing diagram.
5
4–7
for sector address range information.) Drive nCS high
6
7
MSB
23
8
22
9
24-Bit Address
Configuration Handbook, Volume 2
3
28
2
29
1
30
0
31
4–23
CC1