EPCS64 Altera Corporation, EPCS64 Datasheet - Page 13

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Altera Corporation
July 2004
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Read Status Operation
The read status operation code is b'0000 0101, with the MSB listed first.
You can use the read status operation to read the status register.
Figures 4–7
serial configuration devices.
Figure 4–7. EPCS4 Status Register Status Bits
Figure 4–8. EPCS1 Status Register Status Bits
Setting the write in progress bit to 1 indicates that the serial configuration
device is busy with a write or erase cycle. Resetting the write in progress
bit to 0 means no write or erase cycle is in progress.
Resetting the write enable latch bit to 0 indicates that no write or erase
cycle will be accepted. Set the write enable latch bit to 1 before every write
bytes, write status, erase bulk, and erase sector operation.
The non-volatile block protect bits determine the area of the memory
protected from being written or erased unintentionally.
4–10
reference to the block protect bits. The erase bulk operation is only
show the protected area in both serial configuration devices with
Core Version a.b.c variable
Bit 7
Bit 7
and
4–8
show the status bits in the status register of both
Block Protect Bits [2..0]
BP2
BP1
BP1
Block Protect
Configuration Handbook, Volume 2
Bits [1..0]
BP0
BP0
Write Enable
Write Enable
Latch Bit
Latch Bit
WEL
WEL
Progress Bit
Progress Bit
Tables 4–9
Write In
Write In
WIP
WIP
Bit 0
Bit 0
and
4–13