EPCS64 Altera Corporation, EPCS64 Datasheet - Page 22

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Serial Configuration Device Memory Access
4–22
Configuration Handbook, Volume 2
Erase Bulk Operation
The erase bulk operation code is b'1100 0111, with the MSB listed first.
The erase bulk operation sets all memory bits to 1 or 0xFF. Similar to the
write bytes operation, the write enable operation must be executed prior
to the erase bulk operation so that the write enable latch bit in the status
register is set to 1.
Designers implement the erase bulk operation by driving nCS low and
then shifting in the erase bulk operation code on the ASDI pin. nCS must
be driven high after the eighth bit of the erase bulk operation code has
been latched in.
The device initiates the self-timed erase bulk cycle immediately after nCS
is driven high. The self-timed erase bulk cycle usually takes 5 s for EPCS4
devices (guaranteed to be less than 10 s) or 3 s for EPCS1 devices
(guaranteed to be less than 6 s). See t
account for this delay before accessing the memory contents.
Alternatively, designers can check the write in progress bit in the status
register by executing the read status operation while the self-timed erase
cycle is in progress. The write in progress bit is 1 during the self-timed
erase cycle and is 0 when it is complete. The write enable latch bit in the
status register is reset to 0 before the erase cycle is complete.
Figure 4–14. Erase Bulk Operation Timing Diagram
Erase Sector Operation
The erase sector operation code is b'1101 1000, with the MSB listed
first. The erase sector operation allows the user to erase a certain sector in
the serial configuration device by setting all bits inside the sector to 1 or
0xFF. This operation is useful for users who access the unused sectors as
general purpose memory in their applications.
The write enable operation must be executed prior to the erase sector
operation so that the write enable latch bit in the status register is set to 1.
DCLK
ASDI
nCS
Core Version a.b.c variable
Figure 4–14
0
1
shows the timing diagram.
2
Operation Code
3
EB
in
4
Table
5
4–12. Designers must
6
Altera Corporation
7
July 2004