MT28F320A18 Micron Technology, MT28F320A18 Datasheet - Page 26

• Manufacturer Part Number: MT28F320A18
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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READ CYCLE
an access time given by
the data bus and the processor can read the data.
STANDBY MODE
HIGH level on CE# and RP# to enter the standby mode.
In the standby mode, the outputs are placed in High-Z.
Applying a CMOS logic HIGH level on CE# and RP#
reduces the current to I
lected during an ERASE operation or during program-
ming, the device continues to draw current until the
operation is complete.
AUTOMATIC POWER SAVE MODE (APS)
ods when the array is not being read and the device is
in the active mode. During this time, the device
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory
MT28F320A18_F.fm – Rev F 08/03 EN
4
U
Addresses can be accessed in a random order with
When CE# and OE# are LOW, the data is placed on
I
Substantial power savings are realized during peri-
CC
.com
supply current is reduced by applying a logic
CC2
t
AA = 70ns.
(MAX). If the device is dese-
1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
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26
switches to the automatic power saving mode. When
the device switches to this mode, I
I
another operation is initiated. In this mode, the I/O
pins retain the data from the last memory address read
until a new address is initiated. This mode is entered
automatically if no address or control signal toggles.
POWER-UP SEQUENCE
to properly initialize internal chip operations:
should be brought to V
the rise time of RST# (10%–90%) should be < 10µ
CC2
The following power-up sequence is recommended
• At power-up, RST# should be kept at V
• VccQ should not come up before Vcc.
• V
When the power-up sequence is completed, RST#
. The low level of power is maintained until
after V
rity.
PP
should be kept at V
CC
reaches V
IH
CC
. To ensure proper power-up,
(MIN).
IL
to maximize data integ-
2 MEG x 16
CC
©2003 Micron Technology Inc.
is reduced to
IL
for 2µ
S
.
S