MT28F320A18 Micron Technology, MT28F320A18 Datasheet - Page 8

• Manufacturer Part Number: MT28F320A18
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
STATUS REGISTER
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE# by reading the resulting sta-
tus code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the low-
order I/Os (DQ0–DQ7) need to be interpreted.
edge of OE# or CE#, whichever occurs last. Latching
the data prevents errors from occurring if the register
input changes during a status register read.
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be
polled to determine the WSM status. Table 8 defines
the status register bits.
GRAM/ERASE operation, the data appearing on DQ0–
DQ7 remains as status register data until a new com-
mand is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE
OPERATIONS
protection configuration register, read query, read sta-
tus register, clear status register, program, erase, erase
suspend, erase resume, erase confirm, program setup,
alternate program setup, program suspend, program
resume, lock block, unlock block and lock down block,
chip protection register program, and chip protection
register lock. The 8-bit command code is input to the
device on DQ0–DQ7 (see Table 3 for CSM codes and
Table 4 for command definitions). During a PROGRAM
or ERASE cycle, the CSM informs the WSM that a PRO-
GRAM or ERASE cycle has been requested. During a
PROGRAM cycle, the WSM controls the program
sequences and the CSM responds to a PROGRAM SUS-
PEND command only. During an ERASE cycle, the
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory
MT28F320A18_F.fm – Rev F 08/03 EN
4
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The status register allows the user to determine
Register data is updated and latched on the falling
The status register provides the internal state of the
After monitoring the status register during a PRO-
The CSM decodes instructions for read array, read
.com
1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
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CSM responds to an ERASE SUSPEND command only.
When the WSM has completed its task, the WSM status
bit (SR7) is set to a logic HIGH level and the CSM
responds to the full command set. The CSM stays in
the current command state until the microprocessor
issues another command.
GRAM operation only when V
voltage range.
CLEAR STATUS REGISTER
block lock status bit (SR1), the V
program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, a READ
ARRAY command (FFh) must be issued before data
can be read from the memory array, or a READ STATUS
REGISTER command (70h) must be issued to read sta-
tus.
READ OPERATIONS
ARRAY, READ PROTECTION CONFIGURATION REG-
ISTER, READ QUERY and READ STATUS REGISTER.
Read Array
FFh on DQ0–DQ7. Control signals CE# and OE# must
be at a logic LOW level (V
at logic HIGH level (V
Data is available on DQ0–DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial power-
up or device reset, the device defaults to the read array
mode.
The WSM successfully initiates an ERASE or PRO-
The internal circuitry can set, but not clear, the
The following READ operations are available: READ
The array is read by entering the command code
IH
) to read data from the array.
IL
), and WE# and RP# must be
PP
PP
2 MEG x 16
is within its correct
status bit (SR3), the
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