MT28F320A18 Micron Technology, MT28F320A18 Datasheet - Page 7

• Manufacturer Part Number: MT28F320A18
• Description: FLASH MEMORY
• Manufacturer: Micron Technology

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DataSheet
COMMAND STATE MACHINE
machine (CSM) using standard microprocessor write
timings. The CSM acts as an interface between exter-
nal microprocessors and the internal write state
machine (WSM). The available commands are listed in
Table 3, their definitions are given in Table 4 and their
descriptions in Table 5. Program and erase algorithms
are automated by an on-chip WSM. Table 6 shows the
CSM transition states.
entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to con-
trol the device internally and accomplish the
requested operation. A command is valid only if the
exact sequence of WRITE cycles is completed. After the
WSM completes its task, the WSM status bit (SR7) (see
Table 8) is set to a logic HIGH level (1), allowing the
CSM to respond to the full command set again.
OPERATIONS
dard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0–DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals CE# and
WE# must be at a logic LOW level (V
2 Meg x 16, 1.8V Enhanced+ Boot Block Flash Memory
MT28F320A18_F.fm – Rev F 08/03 EN
4
U
Commands are issued to the command state
Once a valid PROGRAM/ERASE command is
Device operations are selected by entering a stan-
.com
Table 3:
COMMAND DQ0–DQ7
40h/10h
B0h
C0h
D0h
20h
50h
60h
70h
90h
98h
FFh
1.8V ENHANCED+ BOOT BLOCK FLASH MEMORY
IL
Command State Machine Codes For
Device Mode Selection
), and OE# and
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CODE ON DEVICE MODE
Program setup/alternate program setup
Block erase setup
Clear status register
Protection configuration setup
Read status register
Read protection configuration register
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume – erase confirm
Read array
7
RP# must be at logic HIGH (V
tion, when needed, can be a WRITE or a READ
depending upon the command. During a READ opera-
tion, control signals CE# and OE# must be at a logic
LOW level (Vil), and WE# and RP# must be at logic
HIGH (V
modes: write, read, reset, standby, and output disable.
cuitry initializes the chip to a read array mode of oper-
ation. Changing the mode of operation requires that a
command code be entered into the CSM. An on-chip
status register is available. The status register allows
the monitoring of the progress of various operations
that can take place on a memory. The status register is
interrogated by entering a READ STATUS REGISTER
command onto the CSM (cycle 1) and reading the reg-
ister data on I/Os DQ0–DQ7 (cycle 2). Status register
bits SR0–SR7 correspond to DQ0–DQ7 (see Table 8).
Command Definition
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command defini-
tions and data for each of the bus cycles.
Table 7 illustrates the bus operations for all the
When the device is powered up, internal reset cir-
Once a specific command code has been entered,
IH
).
IH
). The second opera-
2 MEG x 16
©2003 Micron Technology Inc.