IDT71P73804 Integrated Device Technology, IDT71P73804 Datasheet - Page 15

• Manufacturer Part Number: IDT71P73804
• Description: 1.8v 1m X 18 Ddr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

AC Electrical Characteristics
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
Clock Parameters
Output Parameters
Set-Up Time
Hold Times
18 Mb DDR II SRAM Burst of 4
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
(EIA/JESD65) pg.10
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V). It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
tKC reset
TCQHQV
TCHCQX
TCQHQX
tKC lock
tCHCQV
TCHQX1
Symbol
tKC var
TCHQZ
tKHKH
tKHKH
tKHKH
tKHCH
tCHQV
tCHQX
tDVKH
tKHAX
tKHDX
tKHKL
tKLKH
tAVKH
tIVKH
tKHIX
Cycle to Cycle Period Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K, C→C)
Clock to clock (K→K, C→C)
Clock to data clock (K→C, K→C)
DLL lock time (K,C)
K static to DLL reset
C,C HIGH to output valid
C,C HIGH to output hold
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output HIGH-Z
C HIGH to output LOW-Z
Data-in and BWx/NWx valid to K,K rising edge
K, K rising edge to address hold
K, K rising edge to R, W inputs hold
K, K rising edge to data-in and BWx/NWx hold
Average clock cycle time (K,K,C,C)
Address valid to K,K rising edge
R, W inputs valid to K,K rising edge
Parameter
(V
DD
= 1.8 ± 100mV, V
6.42
1024
-0.45
-0.45
-0.30
-0.45
Min.
4.00
0.00
0.50
0.50
0.35
0.50
0.50
0.35
1.60
1.60
1.80
1.80
15
30
-
-
-
-
-
250MHz
Max
6.30
0.20
1.80
0.45
0.45
0.30
0.45
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DDQ
= 1.4V to 1.9V, T
-0.45
-0.45
-0.35
-0.45
1024
Min.
5.00
2.00
2.00
2.20
2.20
0.00
0.40
0.40
0.6
0.6
0.6
0.6
30
-
-
-
-
-
200MHz
Max
7.88
0.20
2.30
0.45
0.45
0.35
0.45
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Commercial Temperature Range
A
=0 to 70°C )
-0.50
-0.50
-0.40
1024
-0.50
Min.
6.00
2.40
2.40
2.70
2.70
0.00
0.50
0.50
0.7
0.7
0.7
0.7
30
-
-
-
-
-
167MHz
Max
8.40
0.20
2.80
0.50
0.50
0.40
0.50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(3,7)
(3,7)
(3,7)
(3,7)
(3,7)
cycles
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6431 tbl 11
3,4,5
3,4,5
Note
1,5
8
8
9
9
2
3
3
3
3
6
6