IDT71P73804 Integrated Device Technology, IDT71P73804 Datasheet - Page 17

• Manufacturer Part Number: IDT71P73804
• Description: 1.8v 1m X 18 Ddr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

IEEE 1149.1 Test Access Port and Boundary Scan-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access
Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturing and system diagnostics. In conformance with IEEE 1149.1,
the SRAM contains a TAP controller, Instruction register, Bypass Regis-
ter and ID register. The TAP controller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
TAP Controller State Diagram
JTAG Block Diagram
18 Mb DDR II SRAM Burst of 4
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
1
0
TDI
TMS
TCK
Test Logic Reset
Run Test Idle
0
1
1
1
1
Capture DR
Identification Reg.
Update DR
Select DR
Instruction Reg .
Pause DR
Exit 1 DR
Exit 2 DR
Control Signal s
BYPASS Reg.
TAP Controller
Shift DR
0
SRAM
CORE
0
1
0
1
1
0
1
0
0
0
6431 drw 18
1
1
Capture IR
Update IR
Select IR
Pause IR
Exit 1 IR
Exit 2 IR
Shift IR
0
0
1
1
0
1
1
TDO
6431 drw 17
1
0
0
0
0
6.42
17
required. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Instruction Coding
NOTES:
1. Places DQs in Hi-Z in order to sample all input data regardless of
2. TDI is sampled as an input to the first ID register to allow for the serial
3. Bypass register is initialized to Vss when BYPASS instruction is in
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
IR2
0
0
0
0
existing the Shift DR states.
shift of the external TDI data.
1
1
1
1
other SRAM inputs.
voked. The Bypass Register also holds serially loaded TDI when
IR1
0
0
0
0
1
1
1
1
IR0
0
0
0
0
1
1
1
1
SAMPLE/PRELOAD Boundary Scan register
RESERVED
RESERVED
RESERVED
Instruction
SAMPLE-Z
BYPASS
EXTEST
IDCODE
Commercial Temperature Range
Boundary Scan Register
Boundary Scan Register
Identification register
Bypass Register
TDO Output
Do Not Use
Do Not Use
Do Not Use
6431 tbl 13
Notes
2
5
4
5
5
3
1