IDT71P73804 Integrated Device Technology, IDT71P73804 Datasheet - Page 16

• Manufacturer Part Number: IDT71P73804
• Description: 1.8v 1m X 18 Ddr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

Timing Waveform of Combined Read and Write Cycles
NOTE:
1. If R/W is low on the second rising edge of K after a Read request, the device automatically performs a NOP (No Operation.)
2. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent bus
K
DQ
CQ
LD
R/W
CQ
K
SA
C
18 Mb DDR II SRAM Burst of 4
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
C
NOP
contention.
1
tKHCH
Qx3
tKHKL
tIVKH
tKLKH
tAVKH
Read A0
(burst of 4)
A0
2
tKHAX
tKHCH
tKHKH
tKHIX
tCHCQV
tCHCQX
tCHQX1
3
tCHQV
tKHKH
tCHCQX
Read A1
(burst of 4)
Q00
4
A1
Q01
tCHQX
tCHCQV
tCHQV
Q02
5
Q03
NOP
tCQHQV
Note 1
6
tCHQX
Q0
tKHKL
Q1
NOP
(Note 1)
tKLKH
Note 2
7
Q12
6.42
tCQHQX
tCHQZ
16
tKHKH
Q13
Write A2
(burst of 4)
A2
8
tKHKH
tDVKH
tKHDX
D20 D21 D22 D23
9
tDVKH
Write A3
(burst of 4)
10
tKHDX
A3
Commercial Temperature Range
D30 D31 D32 D33
11
Read A4
(burst of 4)
12
A4
6431 drw 09
13
Q40