IDT71P73804 Integrated Device Technology, IDT71P73804 Datasheet - Page 3

• Manufacturer Part Number: IDT71P73804
• Description: 1.8v 1m X 18 Ddr Ii Pipelined Sram
• Manufacturer: Integrated Device Technology

Pin Definitions
NW0, NW1
18 Mb DDR II SRAM Burst of 4
BW
BW
SA
IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit)
Symbol
DQ[X:0]
CQ, CQ
R/W
2
0
SA
0
LD
ZQ
C
K
, BW
, BW
C
K
, SA
1
1
3
Pin Function
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output Clock
Input/Output
Input Clock
Input Clock
Input Clock
Input Clock
Input
Input
Input
Input
Input
Input
Input
Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data outputs are driven
during a valid read operation. The outputs are aligned with the rising edge of both C and C during normal operation. When
operating in a single clock mode (C and C tied high), the outputs are aligned with the rising edge of both K and K. When a
Read operation is not initiated or LD is high (deselected) during the rising edge of K, DQ[X:O] are automatically driven to high
impedance after any previous read operation in progress completes.
1M x 18 -- DQ[17:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks
during write operations. Used to select which byte is written into the device during the current portion of the write operations.
Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written in to the device.
1M x 18 -- BW
Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects. Sampled on the rising
edge of the K and K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered. All the nibble writes are sampled on the same edge as the
data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written in to the
device.
Burst count address bits on x18 and x36 DDRll devices. These bits allow changing the burst order in read or write operations, or
addressing to the individual word of a burst. See page 9 for all possible burst sequences.
Load Control Logic. Sampled on the rising edge of K. If LD is low, a four word burst read or write operation will initiate
designated by the R/W input. If LD is high during the rising edge of K, operations in progress will complete, but new operations
Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new operation should be a
read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write operation will be initiated. If the LD input is
high during the rising edge of K, the R/W input will be ignored.
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
details.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through
DQ[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can
be used as a data valid indication. These signals are free running and do not stop when the output data is three stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. DQ[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V
unconnected.
2M x 8 -- DQ[7:0]
2M x 9 -- DQ[8:0]
512K x 36 -- DQ[35:0]
2M x 9 -- BW
512K x 36 -- BW
2M x 8 -- NW0 controls D[3:0] and NW1 controls D[7:4].
Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.
will not be initiated.
together to deskew the flight times of various devices on the board back to the controller. See application example for further
together to deskew the flight times of various devices on the board back to the controller. See application example for further
through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
0
0
controls DQ[8:0]
controls DQ[8:0] and BW
0
controls DQ[8:0], BW
DDQ
, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left
1
1
controls DQ[17:9], BW
controls DQ[17:9]
6.42
3
Description
2
controls DQ[26:18] and BW
Commercial Temperature Range
3
controls DQ[35:27]
6431 tbl 02a