LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 110

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

System Control
Software Reset Control 1 (SRCR1)
Base 0x400F.E000
Offset 0x044
Type R/W, reset 0x00000000
110
Reset
Reset
Type
Type
Bit/Field
31:27
23:20
15:13
11:9
7:6
26
25
24
19
18
17
16
12
8
5
4
RO
RO
31
15
0
0
Register 28: Software Reset Control 1 (SRCR1), offset 0x044
Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register.
reserved
RO
RO
30
14
0
0
reserved
reserved
reserved
reserved
reserved
TIMER3
TIMER2
TIMER1
TIMER0
COMP2
COMP1
COMP0
reserved
Name
QEI0
I2C0
SSI1
SSI0
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
I2C0
R/W
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
RO
RO
RO
RO
RO
reserved
COMP2
R/W
RO
26
10
0
0
Reset
COMP1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
RO
25
0
9
0
COMP0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset control for analog comparator 2.
Reset control for analog comparator 1.
Reset control for analog comparator 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset control for General-Purpose Timer module 3.
Reset control for General-Purpose Timer module 2.
Reset control for General-Purpose Timer module 1.
Reset control for General-Purpose Timer module 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset control for I2C unit 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset control for QEI unit 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Reset control for SSI unit 1.
Reset control for SSI unit 0.
QEI0
R/W
R/W
24
0
8
0
RO
RO
23
0
7
0
reserved
RO
RO
22
0
6
0
reserved
SSI1
R/W
RO
21
0
5
0
SSI0
R/W
RO
20
0
4
0
reserved
TIMER3
R/W
RO
19
0
3
0
TIMER2
UART2
R/W
R/W
18
0
2
0
June 14, 2007
TIMER1
UART1
R/W
R/W
17
0
1
0
TIMER0
UART0
R/W
R/W
16
0
0
0