LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 398

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

Pulse Width Modulator (PWM)
PWM0 Compare B (PWM0CMPB)
Base 0x4002.8000
Offset 0x05C
Type R/W, reset 0x0000.0000
398
Reset
Reset
Type
Type
Bit/Field
31:16
15:0
R/W
RO
31
15
0
0
Register 29: PWM0 Compare B (PWM0CMPB), offset 0x05C
Register 30: PWM1 Compare B (PWM1CMPB), offset 0x09C
Register 31: PWM2 Compare B (PWM2CMPB), offset 0x0DC
These registers contain a value to be compared against the counter (PWM0CMPB controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an
interrupt (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD
register, then no pulse is ever output.
IF the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL
register), then this 16-bit CompB value is used the next time the counter reaches zero. If the update
mode is synchronous, it is used the next time the counter reaches zero after a synchronous update
has been requested through the PWM Master Control (PWMCTL) register (see page 382). If this
register is rewritten before the actual update occurs, the previous value is never used and is lost.
R/W
RO
30
14
0
0
reserved
CompB
Name
R/W
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
R/W
RO
28
12
0
0
R/W
RO
Type
27
11
R/W
0
0
RO
R/W
RO
26
10
0
0
Reset
0
0
R/W
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
The value to be compared against the counter.
R/W
RO
24
0
8
0
reserved
CompB
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
June 14, 2007
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0