LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 351

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

I2C Master Configuration (I2CMCR)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x020
Type R/W, reset 0x0000.0000
June 14, 2007
Reset
Reset
Type
Type
Bit/Field
31:6
3:1
5
4
0
RO
RO
31
15
0
0
Register 9: I
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
RO
RO
30
14
0
0
reserved
reserved
Name
LPBK
MFE
SFE
RO
RO
29
13
0
0
Luminary Micro Confidential-Advance Product Information
2
RO
RO
28
12
0
0
C Master Configuration (I2CMCR), offset 0x020
RO
RO
Type
27
11
R/W
R/W
R/W
0
0
RO
RO
reserved
RO
RO
26
10
0
0
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I
This bit specifies whether the interface may operate in Slave mode. If
set, Slave mode is enabled; otherwise, Slave mode is disabled.
I
This bit specifies whether the interface may operate in Master mode. If
set, Master mode is enabled; otherwise, Master mode is disabled and
the interface clock is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I
This bit specifies whether the interface is operating normally or in
Loopback mode. If set, the device is put in a test mode loopback
configuration; otherwise, the device operates normally.
RO
RO
2
2
2
24
0
8
0
C Slave Function Enable
C Master Function Enable
C Loopback
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
SFE
R/W
RO
21
0
5
0
MFE
R/W
RO
20
0
4
0
LM3S1150 Microcontroller
RO
RO
19
0
3
0
reserved
RO
RO
18
0
2
0
RO
RO
17
0
1
0
LPBK
R/W
RO
16
0
0
0
351