LM3S1150-IQC50-A1 Luminary Micro, Inc., LM3S1150-IQC50-A1 Datasheet - Page 301

• Manufacturer Part Number: LM3S1150-IQC50-A1
• Description: Microcontroller
• Manufacturer: Luminary Micro, Inc.

13.4
June 14, 2007
4.
5.
As an example, assume the SSI must be configured to operate with the following parameters:
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Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR))
1x106 = 20x106 / (CPSDVSR * (1 + SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1.
2.
3.
4.
5.
Register Map
Table 13-1 on page 302 lists the SSI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that SSI module’s base address:
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Note:
Master operation
Freescale SPI mode (SPO=1, SPH=1)
1 Mbps bit rate
8 data bits
SSI0: 0x4000.8000
SSI1: 0x4000.9000
Write the SSICR0 register with the following configuration:
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Enable the SSI by setting the SSE bit in the SSICR1 register.
Ensure that the SSE bit in the SSICR1 register is disabled.
Write the SSICR1 register with a value of 0x00000000.
Write the SSICPSR register with a value of 0x00000002.
Write the SSICR0 register with a value of 0x000009C7.
The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
Serial clock rate (SCR)
Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
The data size (DSS)
The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control
registers are reprogrammed.
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