FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 154

• Manufacturer Part Number: FDC37C665IR
• Description: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
• Manufacturer: SMSC Corporation

ECP PARALLEL PORT TIMING
Parallel Port FIFO (Mode 101)
The standard parallel port is run at or near the
peak 500Kbytes/sec allowed in the forward
direction using DMA. The state machine does
not examine nAck and begins the next transfer
based on Busy. Refer to Figure 21.
ECP Parallel Port Timing
The timing is designed to allow operation at
approximately 2.0Mbytes/sec over a 15ft cable.
If a shorter cable is used then the bandwidth will
increase.
Forward-Idle
When the host has no data to send it keeps
HostClk (nStrobe) high and the peripheral will
leave PeriphClk (Busy) low.
Forward Data Transfer Phase
The interface transfers data and commands
from the host to the peripheral using an
interlocked
peripheral may indicate its desire to send data
to the host by asserting nPeriphRequest.
PeriphAck
and
HostClk.
The
154
The Forward Data Transfer Phase may be
entered from the Forward-Idle Phase. While in
the
asynchronously
(nFault) to request that the channel be reversed.
When the peripheral is not busy it sets
PeriphAck (Busy) low. The host then sets
HostClk (nStrobe) low when it is prepared to
send data. The data must be stable for the
specified setup time prior to the falling edge of
HostClk. The peripheral then sets PeriphAck
(Busy) high to acknowledge the handshake. The
host then sets HostClk (nStrobe) high. The
peripheral then accepts the data and sets
PeriphAck (Busy) low, completing the transfer.
This sequence is shown in Figure 22.
The timing is designed to provide 3 cable
round-trip times for data setup if Data is driven
simultaneously with HostClk (nStrobe).
Reverse-Idle Phase
The peripheral has no data to send and keeps
PeriphClk high. The host is idle and keeps
HostAck low.
Reverse Data Transfer Phase
The interface transfers data and commands
from the peripheral to the host using an
interlocked HostAck and PeriphClk.
Forward
Phase
assert
the
the
peripheral
nPeriphRequest
may