FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 96

• Manufacturer Part Number: FDC37C665IR
• Description: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
• Manufacturer: SMSC Corporation

EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
Data or Address cycle.
active low when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle
time.
nWAIT is inactive high.
Write Sequence of Operation
1.The host sets PDIR bit in the control register
2.The host selects an EPP register, places data
3.The chip places address or data on PData
4.Chip asserts nDATASTB or nADDRSTRB
5.If nWAIT is asserted, IOCHRDY is deasserted
6.
7.
to a logic "0". This asserts nWRITE.
on the SData bus and drives nIOW active.
bus.
indicating that PData bus contains valid
information, and the WRITE signal is valid.
until the peripheral deasserts nWAIT or a
time-out occurs.
deasserts nDATASTB or nADDRSTRB and
PData bus.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
When the host deasserts nI0W the chip
latches the data from the SData bus for the
The write cycle can complete when
IOCHRDY is driven
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EPP 1.7 Read
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
2.
3.
4.
5.
6.
7.
8.
9.
The host sets PDIR bit in the control
register to a logic "1".
nWRITE and tri-states the PData bus.
The host selects an EPP register and drives
nIOR active.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
If
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating
the termination phase of the cycle.
When the host deasserts nI0R the chip
deasserts nDATASTB or nADDRSTRB.
Peripheral tri-states the PData bus.
Chip
nPDATA in preparation of the next cycle.
that PData is valid and the chip may begin
nWAIT
may modify nWRITE, PDIR
is
asserted,
This deasserts
IOCHRDY
and
is