FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 86

• Manufacturer Part Number: FDC37C665IR
• Description: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
• Manufacturer: SMSC Corporation

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
DLAB = 1
ADDRESS*
REGISTER
Table 37 - Register Summary for an Individual UART Channel
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
REGISTER NAME
86
REGISTER
SYMBOL
MCR
MSR
RBR
THR
FCR
SCR
DLM
LCR
LSR
DDL
IER
IIR
Data Bit 0
(Note 1)
Data Bit 0
Enable
Received Data
Available
Interrupt
(ERDAI)
"0" if Interrupt
Pending
FIFO Enable
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
Data Ready
(DR)
Delta Clear to
Send (DCTS)
Bit 0
Bit 0
Bit 8
BIT 0
Data Bit 1
Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID Bit
RCVR FIFO
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Overrun Error
(OE)
Delta Data Set
Ready
(DDSR)
Bit 1
Bit 1
Bit 9
BIT 1