FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 121

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
Chapter 19 Configuration
19.1
19.1.1 Primary Configuration Address Decoder
Note:
Note 19.1 If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use 10K pull-down.
Note 19.2 The configuration port base address can be relocated through CR26 and CR27.
19.1.2 Entering the Configuration State
SMSC FDC37C672
CONFIG PORT (Note 19.2
INDEX PORT (Note 19.2
DATA PORT
PORT NAME
The Configuration of the FDC37C672 is very flexible and is based on the configuration architecture
implemented in typical Plug-and-Play components. The FDC37C672 is designed for motherboard
applications in which the resources required by their components are known. With its flexible resource
allocation architecture, the FDC37C672 allows the BIOS to assign resources at POST.
System Elements
After a hard reset (RESET_DRV pin asserted) or Vcc Power On Reset the FDC37C672 is in the Run
Mode with all logical devices disabled. The logical devices may be configured through two standard
Configuration I/O Ports (INDEX and DATA) by placing the FDC37C672 into Configuration Mode. The
BIOS uses these configuration ports to initialize the logical devices at POST. The INDEX and DATA ports
are only valid when the FDC37C672 is in Configuration Mode.
The SYSOPT pin is latched on the falling edge of the RESET_DRV or on Vcc Power On Reset to
determine the configuration register's base address. The SYSOPT pin is used to select the CONFIG
PORT's I/O address at power-up. Once powered up the configuration port base address can be changed
through configuration registers CR26 and CR27. The SYSOPT pin is a hardware configuration pin
which is shared with the nRTS1 signal on pin 87. During reset this pin is a weak active low signal which
sinks 30µA.
All I/O addresses are qualified with AEN.
The INDEX and DATA ports are effective only when the chip is in the Configuration State.
The device enters the Configuration State when the following Config Key is successfully written to the
CONFIG PORT.
Config Key = < 0x55 >
)
)
0x03F0
0x03F0
INDEX PORT + 1
(PULL-DOWN RESISTOR)
REFER TO Note 19.1
DATASHEET
SYSOPT= 0
Page 121
0x0370
0x0370
(10K PULL-UP RESISTOR)
SYSOPT= 1
Write
Read/Write
Read/Write
Rev. 10-29-03
TYPE