FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 138

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

SMSC FDC37C672
SMI Status Register 1
Default = 0x00
on Vcc POR
SMI Status Register 2
Default = 0x00
on Vcc POR
Default = 0x00
on VTR POR
Pin Multiplex Controls
Default = 0x06 on Vcc
POR
Force Disk Change
Default = 0x03 on Vcc
POR
Floppy Data Rate
Select Shadow
NAME
REG INDEX
0xB6 R/W
0xB7 R/W
0xB8 R/W
(R/W)
0xC0
0xC1
0xC2
(R)
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] Reserved
Bit[6] Reserved
Bit[7] WDT (Watch Dog Timer)
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
Bit[2] IRINT: This bit is set by a transition on the IR pin
(RDX2 or IRRX as selected in CR L5-F1-B6 i.e., after the
MUX). Cleared by a read of this register.
Bit[3] Reserved
Bit[4] P12: 8042 P1.2. Cleared at source
Bit[7:5] Reserved
Bits[7:0] Reserved
Bit[0] IR Mode Select
Bit[1] DMA 3 Select
Bit[2] Serial IRQ Select
Bit[3] 8042 Select
Bit[4] IRRX 3 Select
Bit[5:7] Reserved
Bit[0] Force Change 0
Bit[1] Force Change 1
Bit[7:2] Reserved
Force Change[1:0] can be written to 1 but are not clearable
by software.
Force Change 1 is cleared on nSTEP and nDS1 Force
Change 0 is cleared on nSTEP and nDS0
DSKCHG (FDC DIR Register, Bit 7) = (nDS0 AND Force
Change 0) OR (nDS1 AND Force Change 1) OR nDSKCHG
Bit[0] Data Rate Select 0
Bit[1] Data Rate Select 1
Bit[2] PRECOMP 0
Bit[3] PRECOMP 1
Bit[4] PRECOMP 2
Bit[5] Reserved
Bit[6] Power Down
Bit[7] Soft Reset
This register is used to read the status of the SMI inputs.
This register is used to read the status of the SMI inputs.
DATASHEET
Page 138
DEFINITION
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
STATE
Datasheet
C,R
C
C
C
C