FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 30

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Note:
SMSC FDC37C672
DMA latency without causing a disk error. Table 6.14 gives several examples of the delays with aFIFO.
The data is based upon the following formula:
At the start of a command, the FIFO action is always disabled and command parameters must be sent
based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is
cleared of any data to ensure that invalid data is not transferred.
An overrun or underrun will terminate the current command and the transfer of data. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove
the remaining data so that the result phase may be entered.
*The 2 Mbps data rate is only available if V
FIFO THRESHOLD
FIFO THRESHOLD
FIFO THRESHOLD
EXAMPLES
EXAMPLES
EXAMPLES
Threshold # x
15 bytes
15 bytes
15 bytes
2 bytes
8 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
1 byte
Table 6.14 -
DATASHEET
DATA RATE
1
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
MAXIMUM DELAY TO SERVICING AT
CC
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FIFO Service Delay
= 5V.
15 x 16 µs - 1.5 µs = 238.5 µs
x 8
15 x 8 µs - 1.5 µs = 118.5 µs
8 x 16 µs - 1.5 µs = 126.5 µs
15 x 4 µs - 1.5 µs = 58.5 µs
1 x 16 µs - 1.5 µs = 14.5 µs
2 x 16 µs - 1.5 µs = 30.5 µs
8 x 4 µs - 1.5 µs = 30.5 µs
2 x 8 µs - 1.5 µs = 14.5 µs
8 x 8 µs - 1.5 µs = 62.5 µs
1 x 4 µs - 1.5 µs = 2.5 µs
2 x 4 µs - 1.5 µs = 6.5 µs
1 x 8 µs - 1.5 µs = 6.5 µs
500 Kbps DATA RATE
2 Mbps* DATA RATE
1 Mbps DATA RATE
- 1.5 µs = DELAY
Enhanced Super I/O Controller with Fast IR
Rev. 10-29-03
Datasheet