FDC37C672QFP SMSC Corporation, FDC37C672QFP Datasheet - Page 129

• Manufacturer Part Number: FDC37C672QFP
• Description: ENHANCED SUPER I/O CONTROLLER WITH FAST IR
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with Fast IR
Datasheet
Note 19.5 A logical device will be active and powered up according to the following equation:
SMSC FDC37C672
Logical Device Control
Memory Base Address
I/O Base Address
(see Device Base I/O
Address Table)
Default = 0x00
on Vcc POR or Reset_Drv
Interrupt Select
Defaults :
0x70 = 0x00,
on Vcc POR or Reset_Drv
0x72 = 0x00,
on Vcc POR or Reset_Drv
DMA Channel Select
Default = 0x04
on Vcc POR or Reset_Drv
32-Bit Memory Space
Configuration
Logical Device
Logical Device Configuration
Reserved
LOGICAL DEVICE
REGISTER
DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET).
The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or
clears the other. If the I/O Base Addr of the logical device is not within the Base I/O range as shown in the
Logical Device I/O map, then read or write is not valid and is ignored.
(0xA9-0xDF)
(0xE0-0xFE)
(0x76-0xA8)
(0x40-0x5F)
(0x60-0x6F)
(0x70,0x72)
(0x71,0x73)
(0x74,0x75)
(0x38-0x3f)
0x60,2,... =
0x61,3,... =
ADDRESS
addr[15:8]
addr[7:0]
0xFF
DATASHEET
Vendor Defined - Reserved - Writes are ignored,
reads return 0.
Reserved - Writes are ignored, reads return 0.
Registers 0x60 and 0x61 set the base address for
the device. If more than one base address is
required, the second base address is set by
registers 0x62 and 0x63.
Refer to Table 19.12 for the number of base
address registers used by each device.
Unused registers will ignore writes and return zero
when read.
0x70 is implemented for each logical device. Refer
to Interrupt Configuration Register description. Only
the keyboard controller uses Interrupt Select
register 0x72. Unused register (0x72) will ignore
writes and return zero when read. Interrupts default
to edge high (ISA compatible).
Reserved - not implemented. These register
locations ignore writes and return zero when read.
Only 0x74 is implemented for FDC, Serial Port 2
and Parallel port. 0x75 is not implemented and
ignores writes and returns zero when read. Refer to
DMA Channel Configuration.
Reserved - not implemented. These register
locations ignore writes and return zero when read.
Reserved - not implemented. These register
locations ignore writes and return zero when read.
Reserved - Vendor Defined (see SMSC defined
Logical Device Configuration Registers).
Reserved
Page 129
DESCRIPTION
Rev. 10-29-03
STATE
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