XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 117

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

DC and Switching Characteristics
Table 17: Timing for the Master and Slave Serial Configuration Modes
14
CCLK
DIN
DOUT
INIT_B
Notes:
1.
2.
PROG_B
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
∆F
(Input)
(Open-Drain)
(Input/Output)
(Input)
(Output)
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
CCSER
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the rising transition
at the CCLK pin
The time from the rising transition at the CCLK pin to the point when
data is last held at the DIN pin
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal at
the CCLK input pin
Variation from the CCLK output frequency set using the ConfigRate
BitGen option
Figure 4: Waveforms for Master and Slave Serial Configuration
Description
T
DCC
Bit 0
No bitstream compression
With bitstream compression
www.xilinx.com
T
CCD
Bit 1
Table
4.
Master
Master
Slave/
Slave
T
Both
Both
Both
CCL
Bit n
1/F
Advance Product Specification
CCSER
T
CCO
All Speed Grades
Bit n-64
Bit n+1
DS312-3 (v1.0) March 1, 2005
–50%
10.0
Min
1.5
5.0
5.0
0
-
-
T
CCH
Bit n-63
+50%
66
Max
12.0
20
-
-
-
-
(2)
DS099-3_04_071604
Units
MHz
MHz
ns
ns
ns
ns
ns
-
R