XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 43

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

Functional Description
36
BCIN[17:0]
A[17:0]
B[17:0]
RSTB
RSTP
RSTA
CEA
CEB
CEP
CLK
Figure 34: MULT18X18SIO Primitive
MULT18X18SIO
B[17:0]
RSTB
RSTB
CEB
CEB
CLK
CLK
BCIN[17:0]
Figure 35: Four Configurations of the B Input
CE
D
CE
D
BREG
BREG
BCOUT[17:0]
RST
RST
BCOUT[17:0]
P[35:0]
BCOUT[17:0]
Q
Q
BREG = 1
B_INPUT = CASCADE
BREG = 1
B_INPUT = DIRECT
DS312-2_28_021205
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The MULT18X18SIO primitive has two additional ports
called BCIN and BCOUT to cascade or share the multi-
plier’s ‘B’ input among several multiplier bocks. The 18-bit
BCIN "cascade" input port offers an alternate input source
from the more typical ‘B’ input. The B_INPUT attribute spec-
ifies whether the specific implementation uses the BCIN or
‘B’ input path. Setting B_INPUT to DIRECT chooses the ‘B’
input. Setting B_INPUT to CASCADE selects the alternate
BCIN input. The BREG register then optionally holds the
selected input value, if required.
BCOUT is an 18-bit output port that always reflects the
value that is applied to the multiplier’s second input, which is
either the ‘B’ input, the cascaded value from the BCIN input,
or the output of the BREG if it is inserted.
Figure 35
different settings for the B_INPUT attribute and the BREG
attribute.
B[17:0]
BCOUT[17:0]
BCOUT[17:0]
BCIN[17:0]
illustrates the four possible configurations using
BREG = 0
B_INPUT = CASCADE
BREG = 0
B_INPUT = DIRECT
DS312-2_29_021505
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Advance Product Specification
DS312-2 (v1.1) March 21, 2005
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