XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 9

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XC3S250E

Manufacturer Part Number
XC3S250E
Description
Spartan-3E FPGA Family
Manufacturer
Xilinx, Inc.
Datasheet

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Functional Description
2
Notes:
1.
2.
ODDROUT1
ODDROUT2
ODDRIN1
ODDRIN2
IDDRIN1
IDDRIN2
OTCLK1
OTCLK2
All IOB signals communicating with the FPGA’s internal logic have the option of inverting polarity inside the IOB.
Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
ICLK1
ICLK2
TCE
OCE
REV
IQ1
ICE
IQ2
T1
T2
SR
O1
O2
T
I
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR REV
SR
SR REV
SR
SR REV
REV
REV
REV
Figure 1: Simplified IOB Diagram
Q
Q
Q
Q
Q
Q
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
www.xilinx.com
Programmable
MUX
DDR
DDR
MUX
Delay
Three-state Path
Input Path
Output Path
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
Advance Product Specification
DS312-2 (v1.1) March 21, 2005
Pull-Up
Down
Pull-
Keeper
Latch
DS312-2_19_030105
V
Pin
I/O Pin
from
Adjacent
IOB
ESD
ESD
V
REF
CCO
I/O
Pin
R

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