XC3S250E Xilinx, Inc., XC3S250E Datasheet - Page 64

• Manufacturer Part Number: XC3S250E
• Description: Spartan-3E FPGA Family
• Manufacturer: Xilinx, Inc.

A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in
multiple-FPGA daisy-chain design equals the sum of the
individual file sizes.
Table 39: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
Table 40: Pin Behavior during Configuration
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
DOUT/BUSY
MOSI/CSI_B
Pin Name
PROG_B
HSWAP
CSO_B
INIT_B
DONE
CCLK
TMS
TDO
TCK
TDI
XC3S1200E
XC3S1600E
M2
M1
M0
D7
D6
D5
D4
XC3S100E
XC3S250E
XC3S500E
Device
R
Table
CCLK (O)
PROG_B
HSWAP
Master
INIT_B
DONE
DOUT
Serial
TMS
TDO
TCK
TDI
39. The configuration file size for a
0
0
0
Number of Configuration
SPI (Serial
CCLK (O)
PROG_B
HSWAP
CSO_B
INIT_B
Flash)
DONE
DOUT
MOSI
TMS
TDO
TCK
1,352,192
2,267,136
3,832,320
5,957,760
TDI
581,344
0
0
1
Bits
BPI (Parallel
NOR Flash)
CCLK (O)
1 = Down
PROG_B
HSWAP
CSO_B
INIT_B
0 = Up
DONE
CSI_B
BUSY
TMS
TDO
TCK
TDI
D7
D6
D5
D4
www.xilinx.com
0
1
Pin Behavior During Configuration
Table 40
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
All I/O pins are high impedance (floating, three-stated, Hi-Z)
during the configuration process. These pins are indicated
in
input is Low, these pins have a pull-up resistor to their asso-
ciated V
After configuration, pull-up and pull-down resistors are
available in the FPGA application as described in
and Pull-Down Resistors, page
Spartan-3E FPGAs have only six dedicated configuration
pins, including the DONE and PROG_B pins, and the four
JTAG boundary-scan pins: TDI, TDO, TMS, and TCK.
PROG_B
Table 40
HSWAP
DONE
JTAG
TMS
TDO
TCK
TDI
1
0
1
CCO
shows how various pins behave during the FPGA
as shaded table entries or cells. If the HSWAP
supply that is active throughout configuration.
PROG_B
CCLK (I)
HSWAP
Parallel
CSO_B
INIT_B
DONE
CSI_B
BUSY
Slave
TMS
TDO
TCK
TDI
D7
D6
D5
D4
1
1
0
Slave Serial
PROG_B
CCLK (I)
HSWAP
INIT_B
DONE
DOUT
9.
TMS
TDO
TCK
Functional Description
TDI
1
1
1
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
I/O Bank
Supply/
0
2
2
2
2
2
2
2
2
2
2
2
2
Pull-Up
57