TN28F010-150 Intel Corporation, TN28F010-150 Datasheet - Page 11

• Manufacturer Part Number: TN28F010-150
• Description: 28F010 1024K (128K X 8) CMOS FLASH MEMORY
• Manufacturer: Intel Corporation

NOTES:
1.
2.
3.
4.
5.
6.
7.
2.2.2.1
While V
memory contents can be accessed via the Read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register
contents are altered.
The default contents of the register upon V
power-up is 00H. This default value ensures that no
spurious alteration of memory contents occurs
during the V
supply is hardwired to the 28F010, the device
powers-up and remains enabled for reads until the
command register contents are changed. Refer to
the AC Characteristics—Read-Only Operations and
waveforms for specific timing parameters.
Read Memory
Read Intelligent
Identifier Codes
Set-Up
Erase/Erase
Erase Verify
Set-Up Program/
Program
Program Verify
Reset
Bus operations are defined in Table 2.
IA = Identifier address: 00H for manufacturer code, 01H for device code.
EA = Erase Address: Address of memory location to be read during erase verify.
PA = Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the WE# pulse.
ID = Identifier Data: Data read from location IA during device identification (Mfr = 89H, Device = B4H).
EVD = Erase Verify Data: Data read from location EA during erase verify.
PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WE#.
PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
Figure 5 illustrates the 28F010 Quick-Erase Algorithm flowchart.
Figure 4 illustrates the 28F010 Quick-Pulse Programming Algorithm flowchart.
The second bus cycle must be followed by the desired command register write.
Command
(7)
PP
(6)
is high, for erasure and programming,
(5)
(5)
PP
Read Command
(6)
(4)
power transition. Where the V
Cycles
Req’d
Bus
1
3
2
2
2
2
2
Operation
Write
Write
Write
Write
Write
Write
Write
Table 3. Command Definitions
First Bus Cycle
(1)
Address
PP
PP
EA
IA
X
X
X
X
X
(2)
2.2.2.2
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer and device codes must be
accessible while the device resides in the target
system. PROM programmers typically access
signature codes by raising A
However, multiplexing high voltage onto address
lines is not a desired system design practice.
The 28F010 contains an intelligent identifier
operation
programming
initiated by writing 90H into the command register.
Following the command Write, a read cycle from
address 0000H retrieves the manufacturer code of
89H. A read cycle from address 0001H returns the
device code of B4H. To terminate the operation, it
Data
A0H
C0H
FFH
00H
90H
20H
40H
(3)
to
Operation
Intelligent Identifier Command
methodology.
supplement
Read
Read
Read
Write
Write
Write
Second Bus Cycle
(1)
Address
9
traditional
The
to a high voltage.
PA
IA
X
X
X
X
operation
(2)
28F010
Data
PROM-
EVD
PVD
FFH
20H
PD
ID
(3)
11
is