TN28F010-150 Intel Corporation, TN28F010-150 Datasheet - Page 9

• Manufacturer Part Number: TN28F010-150
• Description: 28F010 1024K (128K X 8) CMOS FLASH MEMORY
• Manufacturer: Intel Corporation

NOTES:
1.
2.
3.
4.
5.
6.
7.
2.2
The command register is only active when V
high voltage. Depending upon the application, the
system designer may choose to make the V
power supply switchable—available only when
memory updates are desired. When V
contents of the register default to the Read
command, making the 28F010 a read-only memory.
In this mode, the memory contents cannot be
altered.
Or, the system designer may choose to “hardwire”
V
available. In this case, all command register
functions are inhibited whenever V
write lockout voltage V
Power-Up/Down
designed to accommodate either design practice,
and to encourage optimization of the processor
memory interface.
The two-step program/erase write sequence to the
command register provides additional software
write protections.
READ-ONLY
READ/WRITE Output Disable
PP
, making the high voltage supply constantly
Refer to DC Characteristics . When V
Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
V
Read operations with V
With V
Refer to Table 3 for valid data-in during a write operation.
X can be V
ID
is the intelligent identifier high voltage. Refer to DC Characteristics .
Write Protection
PP
at high voltage, the standby current equals I
IL
or V
Read
Output Disable
Standby
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Read
Standby
Write
IH
Protection .)
.
Mode
PP
(5)
LKO
= V
PPH
. (See Section 3.4,
may access array data or the intelligent identifier codes.
The
PP
CC
Table 2. 28F010 Bus Operations
PP
= V
is below the
28F010
= V
(2)
PPL
memory contents can be read but not written or erased.
PPL
(2)
PP
, the
is at
V
V
V
V
V
V
V
V
V
V
CC
PP
is
PP (1)
PPH
PPH
PPH
PPH
PPL
PPL
PPL
PPL
PPL
+ I
PP
(standby).
2.2.1
2.2.1.1
The 28F010 has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins, independent
of device selection. Refer to the AC read timing
waveforms.
When V
used to access array data, to output the intelligent
identifier
program/erase verification. When V
the read operation can only access the array data.
2.2.1.2
With OE# at a logic-high level (V
device is disabled. Output pins are placed in a high-
impedance state.
V
V
A
A
A
A
X
X
X
X
IH
IL
0
0
0
0
V
V
PP
A
A
A
A
ID (3)
ID (3)
X
X
X
X
9
9
9
9
is high (V
BUS OPERATIONS
codes,
Read
Output Disable
CE#
V
V
V
V
V
V
V
V
V
IH
IH
IL
IL
IL
IL
IL
IL
IL
PPH
and
OE# WE#
V
V
V
V
V
V
V
X
X
), the read operation can be
IH
IH
IH
IL
IL
IL
IL
to
V
V
V
V
V
V
V
X
X
IH
IH
IH
IH
IH
IH
IL
access
IH
), output from the
Data Out
Tri-State
Tri-State
Data = 89H
Data = B4H
Data Out
Tri-State
Tri-State
Data In
PP
DQ
is low (V
0
data
28F010
–DQ
(6)
(4)
7
PPL
for
9
),