LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 125

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

June 02, 2008
Bit/Field
11:9
7:6
17
16
15
14
13
12
8
5
4
3
2
reserved
reserved
reserved
reserved
reserved
TIMER1
TIMER0
UART2
Name
QEI0
I2C1
I2C0
SSI1
SSI0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Preliminary
Description
Timer 1 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 1. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
Timer 0 Clock Gating Control. This bit controls the clock gating for
General-Purpose Timer module 0. If set, the unit receives a clock and
functions. Otherwise, the unit is unclocked and disabled. If the unit is
unclocked, reads or writes to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C1 Clock Gating Control. This bit controls the clock gating for I2C
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I2C0 Clock Gating Control. This bit controls the clock gating for I2C
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
QEI0 Clock Gating Control. This bit controls the clock gating for QEI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI1 Clock Gating Control. This bit controls the clock gating for SSI
module 1. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
SSI0 Clock Gating Control. This bit controls the clock gating for SSI
module 0. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART2 Clock Gating Control. This bit controls the clock gating for UART
module 2. If set, the unit receives a clock and functions. Otherwise, the
unit is unclocked and disabled. If the unit is unclocked, reads or writes
to the unit will generate a bus fault.
LM3S3749 Microcontroller
125