LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 624
LM3S3749
Manufacturer Part Number
LM3S3749
Description
Lm3s3749 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S3749.pdf
(753 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LM3S3749-IQC50-A0
Manufacturer:
Texas Instruments
Quantity:
10 000
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Part Number:
LM3S3749-IQC50-A0T
Manufacturer:
Texas Instruments
Quantity:
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Reset
Reset
Type
Type
Pulse Width Modulator (PWM)
PWM Interrupt Status and Clear (PWMISC)
Base 0x4002.8000
Offset 0x01C
Type R/W1C, reset 0x0000.0000
624
Bit/Field
31:20
15:4
19
18
17
16
RO
RO
3
2
1
31
15
0
0
RO
RO
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C
This register provides a summary of the interrupt status of the individual PWM generator blocks. A
bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual
interrupt status registers in each block must be consulted to determine the reason for the interrupt,
and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched
interrupt status.
30
14
0
0
RO
RO
29
13
IntPWM3
IntPWM2
IntPWM1
reserved
IntFault3
IntFault2
IntFault1
IntFault0
reserved
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
RO
RO
RO
RO
26
10
0
0
reserved
reserved
RO
RO
Reset
25
0x00
0x00
0
9
0
0
0
0
0
0
0
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
FAULT3 Interrupt Asserted
Indicates that the FAULT3 input is asserting or the FAULT3 latch has
captured an assertion.
FAULT2 Interrupt Asserted
Indicates that the FAULT2 input is asserting or the FAULT2 latch has
captured an assertion.
FAULT1 Interrupt Asserted
Indicates that the FAULT1 input is asserting or the FAULT1 latch has
captured an assertion.
FAULT0 Interrupt Asserted
Indicates that the FAULT0 input is asserting or the fault condition for
generator 0 is assertng a fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM3 Interrupt Status
Indicates if the PWM generator 3 block is asserting an interrupt.
PWM2 Interrupt Status
Indicates if the PWM generator 2 block is asserting an interrupt.
PWM1 Interrupt Status
Indicates if the PWM generator 1 block is asserting an interrupt.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
IntPWM3
IntFault3
R/W1C
RO
19
0
3
0
IntPWM2
IntFault2
R/W1C
RO
18
0
2
0
IntPWM1
IntFault1
R/W1C
RO
17
0
1
0
June 02, 2008
IntPWM0
IntFault0
R/W1C
RO
16
0
0
0
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