LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 40

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Architectural Overview
1.4.6.2
1.4.6.3
1.4.7
1.4.7.1
1.4.7.2
40
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Flash (see page 161)
The LM3S3749 Flash controller supports 128 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
ROM
The LM3S3749 microcontroller ships with the Stellaris
preprogrammed in read-only memory (ROM). The Stellaris
software library for controlling on-chip peripherals, and includes a boot-loader capability. The library
performs both peripheral initialization and peripheral control functions, with a choice of polled or
interrupt-driven peripheral support, and takes full advantage of the stellar interrupt performance of
the ARM® Cortex™-M3 core. No special pragmas or custom assembly code prologue/epilogue
functions are required. For applications that require in-field programmability, the royalty-free Stellaris
boot loader included in the Stellaris
support in-field firmware updates.
Additional Features
Memory Map (see page 48)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S3749 controller can be found in “Memory Map” on page 48. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
JTAG TAP Controller (see page 54)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing
information on the components. The JTAG Port also provides a means of accessing and controlling
design-for-test features such as I/O pin observation and control, scan testing, and debugging.
The JTAG port is composed of the standard four pins: TCK, TMS, TDI, and TDO. Data is transmitted
serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is
dependent on the current state of the TAP controller. For detailed information on the operation of
the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and
Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
®
Peripheral Driver Library can act as an application loader and
Preliminary
®
family Peripheral Driver Library conveniently
®
Peripheral Driver Library is a royalty-free
June 02, 2008
®