LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 601

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Analog Comparator Control 0 (ACCTL0)
Base 0x4003.C000
Offset 0x24
Type R/W, reset 0x0000.0000
June 02, 2008
Bit/Field
31:12
10:9
11
RO
RO
8
7
31
15
0
0
RO
RO
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44
These registers configure the comparator’s input and output.
30
14
0
0
reserved
RO
RO
29
13
reserved
reserved
0
0
TSLVAL
ASRCP
Name
TOEN
RO
RO
28
12
0
0
TOEN
R/W
RO
27
11
0
0
Type
R/W
R/W
R/W
RO
RO
R/W
RO
26
10
0
0
ASRCP
R/W
RO
Reset
25
0x00
0x00
0
9
0
0
0
0
reserved
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger Output Enable
The TOEN bit enables the ADC event transmission to the ADC. If 0, the
event is suppressed and not sent to the ADC. If 1, the event is
transmitted to the ADC.
Analog Source Positive
The ASRCP field specifies the source of input voltage to the VIN+ terminal
of the comparator. The encodings for this field are as follows:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Trigger Sense Level Value
The TSLVAL bit specifies the sense value of the input that generates
an ADC event if in Level Sense mode. If 0, an ADC event is generated
if the comparator output is Low. Otherwise, an ADC event is generated
if the comparator output is High.
Value
0x0
0x1
0x2
0x3
TSLVAL
R/W
RO
23
0
7
0
Function
Pin value
Pin value of C0+
Internal voltage reference
Reserved
R/W
RO
22
0
6
0
TSEN
R/W
RO
21
0
5
0
ISLVAL
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
LM3S3749 Microcontroller
ISEN
R/W
RO
18
0
2
0
CINV
R/W
RO
17
0
1
0
reserved
RO
RO
16
0
0
0
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