LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 649

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
June 02, 2008
Bit/Field
31:12
11:0
RO
RO
31
15
0
0
RO
RO
Register 55: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 56: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 57: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
Register 58: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset
0x12C
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed; PWM4 is produced from PWM2A with its rising edge delayed;
and PWM6 is produced from PWM3A with its rising edge delayed.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRiseUpd field encoding
in the PWMnCTL register), this 16-bit DBRiseUpd value is used the next time the counter reaches
zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a
synchronous update has been requested through the PWM Master Control (PWMCTL) register
(see page 613). If this register is rewritten before the actual update occurs, the previous value is
never used and is lost.
30
14
0
0
reserved
RiseDelay
RO
RO
29
13
reserved
0
0
Name
RO
RO
28
12
0
0
R/W
RO
27
11
0
0
Type
R/W
RO
R/W
RO
26
10
0
0
R/W
RO
Reset
25
0x00
0
9
0
0
Preliminary
R/W
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
RiseDelay
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
LM3S3749 Microcontroller
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0
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