MT16VDDF12864HG-26A Micron, MT16VDDF12864HG-26A Datasheet - Page 11

• Manufacturer Part Number: MT16VDDF12864HG-26A
• Description: DRAM_Module, high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configuration
• Manufacturer: Micron

Commands
of available commands. For a more detailed descrip-
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
1. DESELECT and NOP are functionally interchangeable.
Table 9:
Used to mask write data; provided coincident with the corresponding data
09005aef80a646bc
DDF16C64_128x64HG_A.fm - Rev. A 3/03 EN
2. BA0–BA1 provide device bank address and A0–A12 provide device row address.
3. BA0–BA1 provide device bank address; A0–A9 (512MB) or A0–A9, A11 (1GB) provide device column address; A10
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for
5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
The Truth Tables below provides a general reference
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
READ bursts with auto precharge enabled and for WRITE bursts.
BA0–BA1 are “Don’t Care.”
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0–A12 provide the
op-code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
11
CS#
tion of commands and operations, refer to the 256Mb
or 512Mb DDR SDRAM component data sheet.
H
L
L
L
L
L
L
L
L
RAS# CAS#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
200-PIN DDR SODIMM
WE#
H
H
H
H
X
L
L
L
L
512MB, 1GB (x64)
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
DM
©2003, Micron Technology Inc.
H
L
ADVANCE
NOTES
6, 7
1
1
2
3
3
4
5
8
Valid
DQS
X