MT16VDDF12864HG-26A Micron, MT16VDDF12864HG-26A Datasheet - Page 19

• Manufacturer Part Number: MT16VDDF12864HG-26A
• Description: DRAM_Module, high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configuration
• Manufacturer: Micron

Notes
09005aef80a646bc
DDF16C64_128x64HG_A.fm - Rev. A 3/03 EN
10. I
11. This parameter is sampled. V
3. Outputs measured with equivalent load:
4. AC timing and I
8. I
1. All voltages referenced to V
2. Tests for AC timing, I
5. The AC and DC input level specifications are as
6. V
7. V
9. Enables on-chip refresh and address counters.
characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.
swing of up to 1.5V in the test environment, but
input timing is still referenced to V
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V
and V
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V
DC value. Thus, from V
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V
system supply for signal termination resistors, is
expected to be set equal to V
variations in the DC level of V
rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for-335 and -265 with the outputs open.
properly initialized, and is averaged at the defined
cycle rate.
V
DD
DD
REF
TT
DD
Q = +2.5V ±0.2V, V
is not applied directly to the device. V
is dependent on output loading and cycle
specifications are tested after the device is
is expected to equal V
IH
(AC).
REF
Output
(V
REF
OUT
bypass capacitor.
may not exceed ±2 percent of the
)
DD
V
DD
tests may use a V
TT
REF
50
, and electrical AC and DC
30pF
Reference
Point
Ω
DD
SS
DD
= V
Q/2, V
.
REF
Q/2 of the transmit-
REF
SS
DD
, f = 100 MHz, =
.
and must track
= +2.5V ±0.2V,
REF
REF
is allowed
(or to the
IL
-to-V
TT
IL
(AC)
is a
IH
19
12. Command/Address input slew rate = 0.5V/ns. For
13. The CK/CK# input reference level (for timing ref-
14. Inputs are not recognized as valid until V
15. The output timing reference level, as measured at
16. tHZ and
17. If DQS transitions to HIGH above V
18. This is not a device limit. The device will operate
19. It is recommended that DQS be valid (HIGH or
20. MIN (
21. The refresh period 64ms. This equates to an aver-
25°C, V
= 0.2V. DM input is grouped with I/O pins, reflect-
ing the fact that they are matched in loading.
-335, -262, -26A, and -265 with slew rates 1V/ns
and faster,
slew rate is less than 0.5V/ ns, timing must be der-
ated:
ns reduction in slew rate from the 500mV/ns.
has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncer-
tain.
erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V
lizes. Exception: during the period before V
stabilizes, CKE £ 0.3 x V
the timing reference point indicated in Note 3, is
V
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
then it must not transition to LOW below V
MIN prior to
with a negative value, but system performance
could be degraded due to bus turnaround.
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on
smallest multiple of
absolute Value for the respective parameter.
(MAX) for I
ple of
value for
age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
.
t
IS has an additional 50ps per each 100mV/
t
RC or
OUT
t
CK that meets the maximum absolute
t
t
LZ transitions occur in the same access
RAS.
(DC) = V
t
DD
IS and
200-PIN DDR SODIMM
t
DQSH (MIN).
t
RFC) for I
t
measurements is the largest multi-
DQSS.
t
512MB, 1GB (x64)
DD
IH are reduced to 900ps. If the
t
CK that meets the minimum
Q/2, V
REF
DD
DD
Q is recognized as LOW.
.
OUT
measurements is the
(peak to peak) T
©2003, Micron Technology Inc.
IH
ADVANCE
(DC) MIN,
REF
IH
stabi-
(DC)
t
RAS
REF
t
IH
A