MT16VDDF12864HG-26A Micron, MT16VDDF12864HG-26A Datasheet - Page 14

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MT16VDDF12864HG-26A

Manufacturer Part Number
MT16VDDF12864HG-26A
Description
DRAM_Module, high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configuration
Manufacturer
Micron
Datasheet
Table 13: I
Notes: 1–5, 8, 10, 12; DDR SDRAM devices only; notes appear on pages 19–22; 0°C £ T
09005aef80a646bc
DDF16C64_128x64HG_A.fm - Rev. A 3/03 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-
Precharge;
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4;
I
per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;
CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
are idle;
control inputs changing once per clock
for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
OPERATING CURRENT: Burst = 2;
burst; One device bank active; Address and control inputs
changing once per clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank
changing once per clock cycle;
and DQS inputs changing twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE £ 0.2V
OPERATING CURRENT: Four device bank interleaving
READs
allowed;
change only during Active READ, or WRITE commands
NOTE:
OUT
a - Value calculated as one module rank in this operating condition, and all other module ranks in I
b - Value calculated reflects all module ranks in this operating condition.
= 0mA; Address and control inputs
(Burst = 4) with auto precharge,
t
t
CK =
CK =
t
RC =
t
t
CK (MIN); Address and control inputs
CK (MIN);
DD
t
RC (MIN);
Specifications and Conditions – 1GB
t
;
RC =
t
active; Address and control inputs
RC =
CKE = HIGH; Address and other
t
t
RC (MIN);
t
CK =
RAS (MAX);
t
t
CK =
CK =
Reads; Continuous
t
t
CK =
CK (MIN); DQ, DM and
t
t
CK (MIN);
CK (MIN); DQ, DM,
cycle. V
t
t
RC = minimum
CK =
t
t
CK =
CK (MIN);
changing once
t
t
t
CK =
RC =
RFC = 7.8125µs
t
CK (MIN);
t
IN
I
CK (MIN);
OUT
t
t
RFC (MIN)
CK (MIN);
= V
= 0mA
REF
t
RC
I
I
I
14
I
I
I
I
DD4W
SYM
DD3N
DD5A
I
I
DD2P
DD3P
DD4R
I
I
I
DD2F
DD0
DD1
DD5
DD6
DD7
-335
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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200-PIN DDR SODIMM
A
MAX
£ +70°C; V
-26A/-
512MB, 1GB (x64)
265
TBD
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DD
, V
DD
-202
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DD
2p (CKE LOW) mode.
Q = +2.5V ±0.2V
©2003, Micron Technology Inc.
UNITS NOTES
ADVANCE
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 42
20, 42
20, 42
20, 44
24, 44
20, 43
44
45
44
41
20
9

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