MT16VDDF12864HG-26A Micron, MT16VDDF12864HG-26A Datasheet - Page 13

• Manufacturer Part Number: MT16VDDF12864HG-26A
• Description: DRAM_Module, high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in a x64 configuration
• Manufacturer: Micron

Table 12: I
Notes: 1–5, 8, 10, 12; DDR SDRAM devices only; notes appear on pages 19–22; 0°C £ T
09005aef80a646bc
DDF16C64_128x64HG_A.fm - Rev. A 3/03 EN
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-
Precharge;
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-
Precharge; Burst = 4;
I
per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;
CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks
are idle;
control inputs changing once per clock
DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;
CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank active
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock
cycle
OPERATING CURRENT: Burst = 2;
One device bank active; Address and control inputs
changing once per clock cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank
changing once per clock cycle;
and DQS inputs changing twice per clock cycle
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE £ 0.2V
OPERATING CURRENT: Four device bank interleaving
READs
allowed;
change only during Active READ, or WRITE commands
NOTE:
OUT
a - Value calculated as one module rank in this operating condition, and all other module ranks in I
b - Value calculated reflects all module ranks in this operating condition.
= 0mA; Address and control inputs
(Burst = 4) with auto precharge,
t
t
CK =
CK =
t
RC =
t
t
CK (MIN); Address and control inputs
CK (MIN);
DD
t
RC (MIN);
Specifications and Conditions – 512MB
t
;
RC =
t
active; Address and control inputs
RC =
CKE = HIGH; Address and other
t
t
RC (MIN);
CK =
t
RAS (MAX);
t
t
CK =
CK =
Reads; Continuous burst;
t
t
CK =
CK (MIN); DQ, DM and
t
t
CK (MIN);
CK (MIN); DQ, DM,
cycle. V
t
t
RC = minimum
CK =
t
t
CK =
CK (MIN);
changing once
t
t
t
CK =
RC =
RFC = 7.8125µs
t
IN
CK (MIN);
t
I
CK (MIN);
OUT
t
t
= V
RFC (MIN)
CK (MIN);
REF
= 0mA
t
for
RC
I
I
13
I
I
I
I
I
I
DD5A
I
I
DD4W
SYM
I
I
DD3N
DD2P
DD2F
DD3P
DD4R
DD5
DD6
DD7
DD0
DD1
a
a
b
b
b
a
b
b
a
b
a
b
1,032
1,392
1,432
1,272
4,080
3,272
Micron Technology, Inc., reserves the right to change products or specifications without notice.
-335
800
480
960
64
96
64
1,032
1,312
1,232
1,112
3,760
2,832
-262
720
400
800
64
96
64
200-PIN DDR SODIMM
A
MAX
£ +70°C; V
-26A/-
512MB, 1GB (x64)
1,192
1,232
1,122
3,760
2,832
265
872
720
400
800
64
96
64
DD
, V
DD
1,272
1,432
1,552
3,920
2,952
-202
992
720
480
800
64
96
64
DD
2p (CKE LOW) mode.
Q = +2.5V ±0.2V
©2003, Micron Technology Inc.
UNITS NOTES
ADVANCE
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
21, 28,
21, 28,
20, 42
20, 42
20, 42
20, 44
24, 44
20, 43
44
45
44
41
20
9