LTC2412 Linear Technology, LTC2412 Datasheet - Page 10

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

LTC2412
PI FU CTIO S
V
a 10 F tantalum capacitor in parallel with 0.1 F ceramic
capacitor as close to the part as possible.
REF
The voltage on these pins can have any value between GND
and V
maintained more positive than the reference negative
input, REF
CH0
CH0
CH1
CH1
The voltage on these four analog inputs (Pins 4 to 7) can
have any value between GND and V
the converter bipolar input range (V
from – 0.5 • (V
the converter produces unique overrange and underrange
output codes.
GND (Pins 8, 9, 10, 15, 16): Ground. Multiple ground pins
internally connected for optimum ground current flow and
V
plane through a low impedance connection. All five pins must
be connected to ground for proper operation.
10
TYPICAL PERFOR A CE CHARACTERISTICS
CC
CC
220
210
190
160
240
230
200
180
170
U
decoupling. Connect each one of these pins to a ground
(Pin 1): Positive Supply Voltage. Bypass to GND with
+
+
+
–
–
–45
Conversion Current
vs Temperature
(Pin 2), REF
CC
(Pin 4): Positive Input for Differential Channel 0.
(Pin 6): Positive Input for Differential Channel 1.
(Pin 5): Negative Input for Differential Channel 0.
(Pin 7): Negative Input for Differential Channel 1.
F
CS = GND
SCK = NC
SDO = NC
O
–30
= GND
as long as the reference positive input, REF
–
U
–15
, by at least 0.1V.
REF
TEMPERATURE ( C)
0
V
V
V
V
CC
CC
CC
CC
) to 0.5 • (V
15
= 5.5V
= 2.7V
–
= 5V
= 3V
(Pin 3): Differential Reference Input.
U
30
45
W
REF
60
75
2412 G37
). Outside this input range
U
90
CC
IN
. Within these limits
= IN
+
1000
900
800
700
600
500
400
300
200
100
– IN
0
Conversion Current
vs Output Data Rate
–
V
IN
IN
SCK = NC
SDO = NC
CS = GND
F
T
O
) extends
REF
A
+
–
10 20 30 40 50
OUTPUT DATA RATE (READINGS/SEC)
= EXT OSC
= 25 C
= GND
= GND
= V
CC
+
, is
V
CC
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
= 5V
V
60 70 80 90
CC
= 3V
2412 G38
100
6
4
3
2
0
5
1
–45
Sleep Mode Current
vs Temperature
–30
–15
CC
TEMPERATURE ( C)
0
) the SDO pin is in a
15
V
V
V
V
CC
CC
CC
CC
30
= 5.5V
= 2.7V
= 5V
= 3V
45
60
F
CS = V
SCK = NC
SDO = NC
O
= GND
75
2412 G39
CC
2412f
90