LTC2412 Linear Technology, LTC2412 Datasheet - Page 25

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
of input multiplexers, wires, connectors or sensors, the
LTC2412 can maintain its exceptional accuracy while
operating with relative large values of source resistance as
shown in Figures 13 and 14. These measured results may
be slightly different from the first order approximation
suggested earlier because they include the effect of the
actual second order input network together with the non-
linear settling process of the input amplifiers. For small C
values, the settling on IN
dently and there is little benefit in trying to match the
source impedance for the two pins.
Larger values of input capacitors (C
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When F
typical differential input resistance is 1.8M which will
generate a gain error of approximately 0.28ppm at full-
scale for each ohm of source resistance driving IN
When F
typical differential input resistance is 2.16M which will
generate a gain error of approximately 0.23ppm at full-
scale for each ohm of source resistance driving IN
When F
quency f
typical differential input resistance is 0.28 • 10
and each ohm of source resistance driving IN
result in 1.78 • 10
effect of the source resistance on the two input pins is
additive with respect to this gain error. The typical +FS and
–FS errors as a function of the sum of the source resis-
tance seen by IN
in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the con-
verter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large C
+
and IN
O
O
O
EOSC
= HIGH (internal oscillator and 50Hz notch), the
= LOW (internal oscillator and 60Hz notch), the
is driven by an external oscillator with a fre-
–
and with the difference between the input and
(external conversion clock operation), the
+
–6
and IN
U
• f
EOSC
–
+
for large values of C
and IN
U
ppm gain error at full-scale. The
–
occurs almost indepen-
W
IN
> 0.01 F) may be
IN
+
IN
are shown
or IN
12
U
capacitor
/f
+
+
EOSC
or IN.
or IN.
–
will
IN
values, it is advisable to carefully match the source imped-
ance seen by the IN
(internal oscillator and 60Hz notch), every 1 mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When F
notch), every 1 mismatch in source impedance trans-
forms a full-scale common mode input signal into a differ-
ential mode input signal of 0.23ppm. When F
an external oscillator with a frequency f
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 1.78 • 10
typical offset error due to input common mode voltage for
Figure 15. +FS Error vs R
Figure 16. –FS Error vs R
–120
–180
–240
–300
300
240
180
120
–60
60
0
0
0 100 200 300 400 500 600 700 800 900 1000
0 100 200 300 400 500 600 700 800 900 1000
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
O
A
CC
O
CC
A
+
–
+
–
= GND
= 25 C
= GND
= 25 C
+
–
= 3.75V
= 1.25V
= 5V
+
= 1.25V
= 3.75V
–
= 5V
= 5V
= GND
= 5V
O
= GND
–6
= HIGH (internal oscillator and 50Hz
+
• f
and IN
R
R
EOSC
SOURCE
SOURCE
SOURCE
SOURCE
C
C
C
ppm. Figure 17 shows the
IN
IN
IN
( )
( )
–
= 0.01 F
= 1 F, 10 F
= 1 F, 10 F
C
C
at IN
at IN
C
pins. When F
IN
IN
IN
= 0.01 F
= 0.1 F
= 0.1 F
+
+
or IN
or IN
LTC2412
2412 F15
2412 F16
EOSC
–
–
(Large C
(Large C
O
is driven by
, every 1
O
= LOW
25
IN
IN
)
)
2412f