LTC2412 Linear Technology, LTC2412 Datasheet - Page 24

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2412
For a simple approximation, the source impedance R
driving an analog input pin (IN
considered to form, together with R
Figure 11), a first order passive network with a time
constant = (R
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant . The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
LTC2412’s front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13 s sampling period.
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that
= 920ns. When an external oscillator of frequency f
used, the sampling period is 2/f
error of less than 1ppm,
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The C
includes the LTC2412 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 13 and 14. A careful implementation can
bring the total input capacitance (C
thus achieving better performance than the one predicted
by Figures 13 and 14. For simplicity, two distinct situa-
tions can be considered.
For relatively small values of input capacitance (C
0.01 F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
24
S
+ R
U
SW
+
) • C
and IN
U
EQ
0.14/f
+
, IN
. The converter is able to
–
EOSC
–
pins as a result of the
IN
EOSC
, REF
O
W
+ C
= LOW or HIGH), the
and, for a settling
SW
.
PAR
+
or REF
and C
) closer to 5pF
PAR
U
capacitor
–
13 s/14
EQ
) can be
EOSC
(see
IN
is
<
S
for C
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C
Figure 13. +FS Error vs R
Figure 14. –FS Error vs R
IN
V
V
INCM
INCM
will deteriorate the converter offset and gain
–10
–20
–30
–40
–50
+ 0.5V
– 0.5V
Figure 12. An RC Network at IN
50
40
30
20
10
0
0
1
1
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
IN
IN
O
A
O
CC
A
CC
+
–
+
–
= GND
= 25 C
= GND
= 25 C
+
–
= 5V
= 2.5V
= 5V
+
–
= GND
= 2.5V
= 5V
IN
= 5V
= GND
= 5V
= GND
10
C
10
C
IN
are unavoidably present as parasitics
IN
R
R
C
C
C
SOURCE
SOURCE
IN
C
IN
= 0.001 F
= 0.001 F
IN
C
C
IN
= 100pF
IN
= 100pF
IN
= 0.01 F
= 0.01 F
R
= 0pF
100
= 0pF
R
100
SOURCE
SOURCE
SOURCE
SOURCE
C
C
( )
( )
IN
IN
1k
1k
at IN
at IN
10k
10k
C
C
+
+
PAR
PAR
20pF
20pF
+
or IN
or IN
and IN
2412 F13
2412 F14
100k
100k
–
–
(Small C
(Small C
IN
IN
LTC2412
+
–
–
2412 F12
IN
IN
)
)
2412f