LTC2412 Linear Technology, LTC2412 Datasheet - Page 14

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC2412
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is the selected channel indicator.
The bit is LOW for channel 0 and HIGH for channel 1
selected.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2412 Status Bits
Input Range
V
0V V
–0.5 • V
V
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
14
IN
IN
< – 0.5 • V
0.5 • V
IN
REF
< 0.5 • V
REF
V
REF
IN
REF
< 0V
SDO
SCK
CS
IN
SLEEP
is >0, this bit is HIGH. If V
U
Hi-Z
U
BIT 31
EOC
1
Bit 31
EOC
0
0
0
0
CH0/CH1
BIT 30
W
CH0/CH1
Bit 30
0 or 1
0 or 1
0 or 1
0 or 1
2
BIT 29
IN
SIG
Bit 29 Bit 28
Figure 3. Output Data Timing
SIG
is <0, this
U
3
1
1
0
0
BIT 28
MSB
MSB
1
0
1
0
4
DATA OUTPUT
BIT 27
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the analog input pins is main-
tained within the – 0.3V to (V
operating range, a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
5
26
REF
. For differential input voltages greater than
LSB
BIT 5
24
27
BIT 0
IN
CC
32
from –FS = –0.5 • V
+ 0.3V) absolute maximum
CONVERSION
2412 F03
REF
2412f
to