LTC2412 Linear Technology, LTC2412 Datasheet - Page 27

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
100 of source resistance driving REF
into about 1.34ppm additional INL error. When F
(internal oscillator and 50Hz notch), every 100 of source
resistance driving REF
1.1ppm additional INL error. When F
external oscillator with a frequency f
source resistance driving REF
about 8.73 • 10
Figure 22 shows the typical INL error due to the source
resistance driving the REF
values are used. The effect of the source resistance on the
Figure 20. +FS Error vs R
Figure 18. +FS Error vs R
O
= LOW (internal oscillator and 60Hz notch), every
–180
–270
–360
–450
–10
–20
–30
–40
–50
–90
0
0
1
0 100 200 300 400 500 600 700 800 900 1000
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
O
CC
A
O
A
CC
+
–
+
= GND
= 25 C
–
= GND
= 25 C
+
= 5V
–
= 2.5V
= 5V
+
–
= 3.75V
= 1.25V
= 5V
= 5V
= GND
C
–6
= 5V
= GND
10
REF
C
U
REF
C
C
= 0.001 F
• f
REF
REF
= 100pF
SOURCE
+
= 0.01 F
= 0pF
100
R
R
EOSC
SOURCE
SOURCE
SOURCE
or REF
U
+
or REF
C
ppm additional INL error.
at REF
REF
( )
( )
1k
at REF
+
C
= 1 F, 10 F
C
REF
–
or REF
REF
–
translates into about
+
W
= 0.01 F
pins when large C
= 0.1 F
10k
+
EOSC
and REF
+
or REF
O
or REF
2412 F18
2412 F20
–
is driven by an
, every 100 of
100k
translates into
–
–
(Small C
(Large C
–
U
translates
O
= HIGH
IN
REF
REF
)
)
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF
and REF
user is thus advised to minimize the combined source
impedance driving the REF
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
Figure 21. –FS Error vs R
Figure 19. –FS Error vs R
–
pins does not help the gain or the INL error. The
450
360
270
180
50
40
30
20
10
90
0
0
1
0 100 200 300 400 500 600 700 800 900 1000
V
REF
REF
IN
IN
F
T
V
REF
REF
IN
IN
F
T
O
A
CC
O
A
CC
+
–
+
= GND
= 25 C
–
= GND
= 25 C
+
–
= GND
= 5V
= 2.5V
+
–
= 1.25V
= 3.75V
= 5V
= 5V
C
= GND
= 5V
= GND
10
REF
C
C
REF
REF
C
= 0.001 F
REF
= 100pF
= 0.01 F
SOURCE
= 0pF
100
R
R
SOURCE
SOURCE
SOURCE
+
C
and REF
REF
at REF
( )
( )
1k
C
at REF
REF
= 1 F, 10 F
C
REF
= 0.01 F
+
10k
= 0.1 F
+
and REF
–
or REF
pins rather than to
2412 F19
LTC2412
2412 F21
100k
–
–
(Small C
(Large C
27
IN
REF
2412f
)
)
+