LTC2412 Linear Technology, LTC2412 Datasheet - Page 19

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
typically 1ms after V
SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 32nd falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
(EXTERNAL)
SDO
SCK
CS
CONVERSION
U
CC
exceeds 2V. The level applied to
U
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
W
BIT 31
EOC
ANALOG INPUT RANGE
CH0/CH1
BIT 30
–0.5V
REF
U
TO 0.5V
0.1V TO V
REFERENCE
BIT 29
VOLTAGE
SIG
1 F
2.7V TO 5.5V
REF
CC
BIT 28
MSB
1
2
3
4
5
6
7
DATA OUTPUT
V
REF
REF
CH0
CH0
CH1
CH1
CC
LTC2412
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state during the EOC test. In
order to allow the device to return to the low power sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
and the device begins outputting data at time t
the falling edge of CS (if EOC = 0) or t
LOW (if CS is LOW during the falling edge of EOC). The
value of t
oscillator (F
external oscillator of frequency f
3.6/f
+
–
+
–
+
–
BIT 27
SDO
GND
SCK
EOSC
CS
F
O
14
13
12
11
BIT 26
. If CS is pulled HIGH before time t
EOCtest
8, 9, 10, 15, 16
0
= logic LOW or HIGH). If F
2-WIRE
INTERFACE
V
CC
is 23 s if the device is using its internal
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
LSB
BIT 5
24
EOSC
EOCtest
, then t
LTC2412
BIT 0
O
is driven by an
after EOC goes
EOCtest
EOCtest
CONVERSION
EOCtest
19
, the
after
2412f
2412 F07
is