LTC2412 Linear Technology, LTC2412 Datasheet - Page 21

• Manufacturer Part Number: LTC2412
• Description: 2-Channel Differential Input 24-Bit No Latency DS ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
(INTERNAL)
SDO
SCK
SLEEP
CS
Hi-Z
> t
OUTPUT
DATA
EOCtest
BIT 0
EOC
U
CONVERSION
Hi-Z
TEST EOC
CC
U
exceeds 2V. An internal weak
Hi-Z
Figure 9. Internal Serial Clock, Reduced Data Output Length
SLEEP
(OPTIONAL)
W
TEST EOC
SLEEP
ANALOG INPUT RANGE
–0.5V
Hi-Z
<t
REF
EOCtest
U
BIT 31
TO 0.5V
0.1V TO V
REFERENCE
EOC
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
CH0/CH1
BIT 30
1
2
3
4
5
6
7
V
REF
REF
CH0
CH0
CH1
CH1
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the
first rising edge of SCK and ends after the 32nd rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
CC
LTC2412
+
–
+
–
+
–
BIT 29
SIG
GND
SDO
SCK
CS
F
O
DATA OUTPUT
14
13
12
11
8, 9, 10, 15, 16
BIT 28
MSB
3-WIRE
SPI INTERFACE
BIT 27
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
BIT 26
BIT 8
LTC2412
V
CC
10k
CONVERSION
Hi-Z
TEST EOC
21
2412f
2412 F09