spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 105

• Manufacturer Part Number: spd6722qcce
• Description: Isa-to-pc-card Pcmcia Controllers
• Manufacturer: Intel Corporation

Datasheet
1. AEN must be inactive for t
2. Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
3. Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
4. If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
5. Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
Symbol
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
Table 26. ISA Bus Timing (Sheet 2 of 2)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2a
4a
6a
6b
10
11
12
13
14
15
16
17
18
19
20
3
4
5
7
8
9
IOCS16* inactive delay from SA[15:0]
SA[16:0], SBHE* setup to any Command active
LA[23:17] latching by ALE to any Command active
Any Command active to IOCHRDY inactive (low)
IOCHRDY three-state from Command inactive
MEMCS16* inactive delay from unlatched LA[23:17]
IOW* or IOR* pulse width
MEMW* or MEMR* pulse width
Any Command inactive to next Command active
Address or SBHE* hold from any Command inactive
Data valid from MEMW* active
Data valid from IOW* active
Data hold from MEMW* inactive
Data hold from IOW* inactive
Data delay from IOR* active, for internal registers
Data delay from IOCHRDY active
Data hold from IOR* or MEMR* inactive
AEN inactive setup to valid IOR* or IOW* active
AEN hold from IOR* or IOW* inactive
REFRESH* inactive setup to valid MEMR* or MEMW* active
REFRESH* inactive hold from MEMR* or MEMW* active
MEMCS16* active delay from SA[16:12] valid
*ZWS delay from MEMW* active
*ZWS hold from MEMW* inactive
2
, t
3
, and t
1
6
timing specifications to be applicable.
Parameter
5
1
1
ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
4
1, 2
3
MIN
140
180
100
30
90
40
40
5
0
5
5
0
5
0
0
MAX
130
40
40
30
40
40
15
30
40
30
15
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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