spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 68

• Manufacturer Part Number: spd6722qcce
• Description: Isa-to-pc-card Pcmcia Controllers
• Manufacturer: Intel Corporation

PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
9.6
68
Register Name: Card Memory Map 0–4 Offset Address High
Index: 15h, 1Dh, 25h, 2Dh, 35h
Write Protect
RW:0
Bit 7
REG Setting
Bits 7:0 — Offset Address 19:12
This register contains the least-significant byte of the quantity that will be added to the host
memory address, which will determine where the memory access will occur in the PC Card
memory map.
The most-significant six bits are located in the Card Memory Map 0–4 Offset Address High
register (see
Card Memory Map 0–4 Offset Address High
There are five separate Card Memory Map Offset Address High registers, each with identical
fields. These registers are located at the following indexes:
Bits 5:0 — Offset Address 25:20
This field contains the most-significant six bits of the Offset Address. See the description of the
Offset Address field associated with bits 7:0 of the Card Memory Map 0–4 Offset Address Low
register (see
Bit 6 — REG Setting
This bit determines whether -REG (
Card Information Structure (CIS) memory is accessed by setting this bit to ‘1’.
RW:0
Bit 6
0
1
Index
15h
1Dh
25h
2Dh
35h
“Card Memory Map 0–4 Offset Address High” on page
“Card Memory Map 0–4 Offset Address Low” on page
-REG (see
-REG is active for accesses made through this window.
Bit 5
Card Memory Map Offset Address High
Card Memory Map 0 Offset Address High
Card Memory Map 1 Offset Address High
Card Memory Map 2 Offset Address High
Card Memory Map 3 Offset Address High
Card Memory Map 4 Offset Address High
Table 2 on page
Bit 4
Table
20) is not active for accesses made through this window.
2) will be active for accesses made through this window.
Offset Address 25:20
Bit 3
RW:000000
Bit 2
67).
68).
Register Compatibility Type: 365
Bit 1
Register Per: socket
Datasheet
Bit 0