spd6722qcce Intel Corporation, spd6722qcce Datasheet - Page 86
spd6722qcce
Manufacturer Part Number
spd6722qcce
Description
Isa-to-pc-card Pcmcia Controllers
Manufacturer
Intel Corporation
Datasheet
1.SPD6722QCCE.pdf
(138 pages)
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PD6710/’22 — ISA-to-PC-Card (PCMCIA) Controllers
11.3
86
Register Name: Recovery Timing 0–1
Index: 3Ch, 3Fh
Recovery Prescalar Select
Bit 7
RW:00
Bits 5:0 — Command Multiplier Value
This field indicates an integer value N
7:6) to control the length that a command is active.
Bits 7:6 — Command Prescalar Select
This field chooses one of four prescalar values N
Command Multiplier Value (bits 5:0) to control the length that a command is active.
Recovery Timing 0–1
There are two separate Recover Timing registers, each with identical fields. These registers are
located at the following indexes:
The Recovery Timing register for each timing set controls how long a PC Card cycle’s command
(that is, -OE, -WE, -IORD, -IOWR; see
number of internal clock cycles.
The overall command recovery timing length R is programmed by selecting a 2-bit prescaling
value (bits 7:6 of this register) representing weights of 1, 16, 256, or 8192, and then selecting a
multiplier value (bits 5:0) to which that prescalar is multiplied to produce the overall command
recovery timing length according to the following formula:
The value of R, representing the number of internal clock cycles for command recovery, is then
multiplied by the internal clock’s period to determine the command recovery time (see
Bus Timing Calculations” on page 109
00
01
10
11
Bit 6
N pres = 1
N pres = 16
N pres = 256
N pres = 8192
Index
3Ch
3Fh
Bit 5
Recovery Timing
Recovery Timing 0
Recovery Timing 1
R = (N
pres
N
Bit 4
val
) + 1
val
for further discussion).
Table 2 on page
from 0 to 63; it is combined with a prescalar value (bits
Recovery Multiplier Value
Bit 3
pres
RW:000011
that are combined with the value of the
20) recovery will be, in terms of the
Bit 2
Register Compatibility Type: 365
Bit 1
Register Per: socket
Datasheet
“PC Card
Bit 0
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