upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 364
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upd78f0114hgb-8es-a
Manufacturer Part Number
upd78f0114hgb-8es-a
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0114HGB-8ES-A.pdf
(505 pages)
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20.4 Cautions for Power-on-Clear Circuit
voltage (V
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
software counter that uses a timer, and then initialize the ports.
364
Note 1
If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
In a system where the supply voltage (V
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
Notes 1.
POC
2.
3.
), the system may be repeatedly reset and released from the reset status. In this case, the time from
No
If reset is generated again during this period, initialization processing is not started.
A flowchart is shown on the next page.
Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is
selected as the high-speed system clock by the option byte.
switched without reading the OSTC value.
Figure 20-3. Example of Software Processing After Release of Reset (1/2)
50 ms has passed?
Change CPU clock
Check stabilization
Checking cause
(TMIFH1 = 1?)
(set to 50 ms)
of oscillation
of reset
Initialization
processing
Start timer
Reset
Power-on-clear
Yes
Note 2
CHAPTER 20 POWER-ON-CLEAR CIRCUIT
DD
User’s Manual U16961EJ4V0UD
) fluctuates for a certain period in the vicinity of the POC detection
; The internal oscillation clock is set as the CPU clock when
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
; 8-bit timer H1 can operate with the internal oscillation clock.
; Check the stabilization of oscillation of the high-speed system clock by using
; Change the CPU clock from the internal oscillation clock
; TMIFH1 = 1: Interrupt request is generated.
; Initialization of ports
the reset signal is generated
can be identified by the RESF register.
Source: f
(f
the OSTC register
to the high-speed system clock.
R
: internal oscillation clock frequency)
R
(480 kHz (MAX.))/2
Note 3
.
7
compare value 200 = 53 ms
Therefore, the CPU clock can be
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