upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 499

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Option
Byte
Flash
Memory
On-chip
Debug
Function
Function
0084H/1084H
0081H/1081H,
0082H/1082H,
0083H/1083H
0080H/1080H
IMS: Memory
size switching
register
UART6
Flash-
programming
mode control
register
(FLPMC)
When using X1
and X2 pins
PD78F0114HD The PD78F0114HD has an on-chip debug function. Do not use this product for
Details of
Function
Be sure to set 00H (disabling on-chip debug operation) to 0084H for products not
equipped with the on-chip debug function ( PD78F0112H, 78F0113H,
78F0114H). Also set 00H to 1084H because 0084H and 1084H are switched at
boot swapping.
To use the on-chip debug function with a product equipped with the on-chip debug
function ( PD78F0114HD), set 02H or 03H to 0084H. Set a value that is the
same as that of 0084H to 1084H because 0084H and 1084H are switched at boot
swapping.
Be sure to set 00H to 0081H, 0082H, and 0083H (0081H/1081H, 0082H/1082H,
and 0083H/1083H when the boot swap function is used).
If LSROSC = 0 (oscillation can be stopped by software), the count clock is not
supplied to the watchdog timer in the HALT and STOP modes, regardless of the
setting of bit 0 (RSTOP) of the internal oscillation mode register (RCM). When 8-
bit timer H1 operates with the internal oscillation clock, the count clock is supplied
to 8-bit timer H1 even in the HALT/STOP mode.
Be sure to clear bit 2 to 7 to 0.
There are differences in noise immunity and noise radiation between the flash
memory and mask ROM versions. When pre-producing an application set with
the flash memory version and then mass-producing it with the mask ROM version,
be sure to conduct sufficient evaluations for the commercial samples (not
engineering samples) of the mask ROM versions.
The initial value of IMS is "setting prohibited (CFH)". Be sure to set each product
to the values shown in Table 23-2 at initialization. Also, when using the
78K0/KC1+ to evaluate the program of a mask ROM version of the 78K0/KC1, be
sure to set the values shown in Table 23-2.
When UART6 is selected, the receive clock is calculated based on the reset
command sent from the dedicated flash programmer after the FLMD0 pulse has
been received.
Be sure to keep FWEDIS at 0 until writing or erasing of the flash memory is
completed.
Make sure that FWEDIS = 1 in the normal mode.
Manipulate FLSPM1 and FLSPM0 after execution branches to the internal RAM.
The address of the flash memory is specified by an address signal from the CPU
when FLSPM1 = 0 or the set value of the firmware written when FLSPM1 = 1. In
the on-board mode, the specifications of FLSPM1 and FLSPM0 are ignored.
mass production because its reliability cannot be guaranteed after the on-chip
debug function has been used, given the issue of the number of times the flash
memory can be rewritten. NEC Electronics does not accept complaints
concerning this product.
Input the clock from the X1 pin during on-chip debugging.
Control the X1 and X2 pins by externally pulling down the P31 pin.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16961EJ4V0UD
Cautions
p. 378
p. 378
p. 378
p. 379
p. 379
p. 381
p. 382
p. 396
p. 400
p. 400
p. 400
p. 408
p. 408
p. 408
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