upd78f0114hgb-8es-a Renesas Electronics Corporation., upd78f0114hgb-8es-a Datasheet - Page 99

• Manufacturer Part Number: upd78f0114hgb-8es-a
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

<R>
Notes 1.
Caution Be sure to clear bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
Address: FFFBH
Symbol
PCC
2.
3.
4.
5.
2. f
3. f
4. f
5. f
Bit 5 is read-only.
When the CPU is operating on the subsystem clock, MCC should be used to stop the high-speed
system clock oscillator operation. When the CPU is operating on the internal oscillation clock, use bit 7
(MSTOP) of the main OSC control register (MOC) to stop the high-speed system clock oscillator
operation (this cannot be set by MCC). A STOP instruction should not be used.
Clear this bit to 0 when the subsystem clock is used, and set it to 1 when the subsystem clock is not
used.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Setting is prohibited for the (A1) grade products.
X
R
XP
XT
:
:
CSS
:
:
MCC
MCC
FRC
CLS
<7>
0
1
0
1
0
1
0
1
Note 4
After reset: 00H
Main system clock oscillation frequency (high-speed system clock oscillation frequency or
internal oscillation clock oscillation frequency)
Internal oscillation clock oscillation frequency
High-speed system clock oscillation frequency
Subsystem clock oscillation frequency
Figure 5-2. Format of Processor Clock Control Register (PCC)
Oscillation possible
Oscillation stopped
On-chip feedback resistor used
On-chip feedback resistor not used
High-speed system clock or internal oscillation clock
Subsystem clock
PCC2
FRC
<6>
Other than above
0
0
0
0
1
0
0
0
0
1
R/W
CHAPTER 5 CLOCK GENERATOR
PCC1
Control of high-speed system clock oscillator operation
CLS
<5>
Note 1
User’s Manual U16961EJ4V0UD
0
0
1
1
0
0
0
1
1
0
Subsystem clock feedback resistor selection
PCC0
CSS
<4>
0
1
0
1
0
0
1
0
1
0
CPU clock status
f
f
f
f
f
f
Setting prohibited
X
X
X
X
X
XT
/2
/2
/2
/2
/2
2
3
4
3
0
CPU clock (f
PCC2
f
f
Setting prohibited
Setting prohibited
Setting prohibited
2
R
R
/2
MCM0 = 0
Note 5
Note 3
CPU
) selection
PCC1
Note 2
1
f
f
f
f
f
XP
XP
XP
XP
XP
/2
/2
/2
/2
MCM0 = 1
2
3
4
PCC0
0
99